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dual , 256 - position , spi digital potentiometer ad5162 r ev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of t hird parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2003 C 2010 analog devices, i nc. all rights reserved. features 2- channel, 256 - position potentiometer end - to - end resistance: 2.5 k ? , 10 k ? , 50 k ? , and 100 k ? compact 10 - lead msop (3 mm 4.9 mm) package fast settling time: t s = 5 s typical on power - up full read/write of wiper register power - on preset to m idscale computer software replaces microcontroller in factory programming applications single supply: 2.7 v to 5.5 v low temperature coefficient: 35 ppm/c low power: i dd = 6 a maximum wide operating temperature: ? 40c to +125c evaluation board avai lable qualified for automotive applications applications systems calibrations electronics level settings mechanical trimmers replacement in new designs permanent factory pcb setting transducer adjustment of pressure, temperature, position, chemical, and optical sensors rf amplifier biasing automotive electronics adjustment gain control and offset adjustment functional block dia gram a1 a = 0 a = 1 v dd gnd sdi clk cs w1 wiper register 1 spi inter f ac e ad5162 04108-0-001 b1 w2 w iper register 2 b2 figure 1. general description the ad5162 provides a compact 3 mm 4.9 mm packaged sol ution for dual , 256- position adjustment applications. this device per forms the same electronic adjustment function as a 3- terminal mechanical potentiometer. available in four end - to - end resistance values (2.5 k ?, 10 k?, 50 k?, 100 k?), this low temperature coefficient device is ideal f or high accuracy and stability - variable resistance adjustments. the wiper settings are controllable through an spi digital interface. the resistance between the wiper and either endpoint of the fixed resistor varies linearly w ith respect to the digital code transferred into the rdac latch. 1 operating from a 2.7 v to 5.5 v power supply and consuming less than 6 a allows the ad5162 to be used in portable battery - operated applications. for applications that program the ad5162 at the factory, analog devices offers device programming software running on windows? nt/2000/xp operating systems. this software effectively replaces the need for external spi controllers, which in turn enhances the time to market of systems. an ad5162 eva luation kit and software are available. the kit includes a cable and instruction manual. 1 the terms digital potentiometer , vr , and rdac are used interchangeably.
ad5162 rev. c | page 2 of 20 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 electrical characteristic s: 2.5 k ? ve rsion ................................. 3 electrical characteristics: 10 k ? , 50 k? , and 100 k? ve rsions ......................................................................................................... 4 timing characteristics: all versions ......................................... 5 absolute maximum ratings ............................................................ 6 esd caution .................................................................................. 6 pin configuration and functi on descriptions ............................. 7 typical performance characteristics ............................................. 8 test circuits ..................................................................................... 12 theory of operation ...................................................................... 13 programming the variable resistor and voltage ................... 13 programming the potentiometer divider ............................... 14 esd protection ........................................................................... 14 terminal voltage operating range ......................................... 14 power - up sequenc e ................................................................... 14 layout and power supply bypassing ....................................... 15 constant bias to retain resistance setting ............................. 15 evaluation board ........................................................................ 15 spi interface .................................................................................... 16 spi - compatible, 3 - wire serial bus .......................................... 16 outline dimensions ....................................................................... 17 ordering guide .......................................................................... 17 automotive products ................................................................. 17 revision history 12/10 rev. b to rev.c added automotive parts to features section ............................... 1 added automotive products paragraph ...................................... 17 4 /09 rev. a to rev. b changes to features section ............................................................ 1 changes to dc characteristics r heostat mode parameter and to dc characteristi cs potentiometer divider mode parameter, table 1 ................................................................................................ 3 updated outline dimensions ....................................................... 17 changes to ordering guide .......................................................... 17 11/03 rev. 0 to rev. a changes to electrical characteristics ............................................ 3 11/03 revision 0: initial version
ad5162 rev. c | page 3 of 20 specifications electrical character istics : 2.5 k? version v dd = 5 v 10%, or 3 v 10%; v a = v dd ; v b = 0 v; ?40c < t a < +125c; unless otherwise noted. table 1 . parameter symbol conditions min typ 1 max unit dc characteristics rheostat mode resistor differential nonlinearity 2 r- dnl r wb , v a = no connect ? 2 0.1 +2 lsb resistor integral nonlinearity 2 r- inl r wb , v a = no connect ? 14 2 + 14 lsb nominal resistor tolerance 3 ?r ab t a = 25c ? 20 +55 % resistance temperature coefficient ( ?r ab /r ab )/ ?t v ab = v dd , wiper = no connect 35 ppm/c wiper resistance r wb code = 0x00, v dd = 5 v 160 200 ? dc characteristics potentiometer divider mode 4 differential nonlinearity 5 dnl ? 1.5 0.1 +1.5 lsb integral no nlinearity 5 inl ? 2 0.6 +2 lsb voltage divider temperature coefficient ( ?v w /v w )/ ?t code = 0x80 15 ppm/c full - scale error v wfse code = 0xff ? 14 ?5 .5 0 lsb zero - scale error v wzse code = 0x00 0 4.5 12 lsb resistor terminals voltage range 6 v a , v b , v w gnd v dd v capacitance a, b 7 c a , c b f = 1 mhz, measured to gnd, code = 0x80 45 pf capacitance w 7 c w f = 1 mhz, measured to gnd, code = 0x80 60 pf c ommon - mode leakage i cm v a = v b = v dd /2 1 na digital inputs and outputs input logic high v ih v dd = 5 v 2.4 v input logic low v il v dd = 5 v 0.8 v input logic high v ih v dd = 3 v 2.1 v input logic low v il v dd = 3 v 0.6 v input current i il v in = 0 v or 5 v 1 a input capacitance 7 c il 5 pf power supplies power supply range v dd range 2.7 5.5 v supply current i dd v ih = 5 v or v il = 0 v 3.5 6 a power diss ipation 8 p diss v ih = 5 v or v il = 0 v, v dd = 5 v 30 w power supply sensitivity pss v dd = 5 v 10%, code = midscale 0.02 0.08 %/% dynamic characteristics 9 bandwidth , ? 3 db bw code = 0x80 4.8 mhz total harmonic distortion thd w v a = 1 v rms, v b = 0 v, f = 1 khz 0.1 % v w settling time t s v a = 5 v, v b = 0 v, 1 lsb error band 1 s resistor noise voltage density e n_wb r wb = 1.25 k ? , r s = 0 3.2 nv/ hz 1 typical specifications represent average readings at 25c and v dd = 5 v. 2 resistor position nonlinearity error , r- inl , is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. r - dnl measures the relative step change from the ideal between successive tap positions. parts are guaranteed monotonic. 3 v a = v dd , v b = 0 v, wiper (v w ) = no connect. 4 specifications apply to all vrs . 5 inl and dnl are measured at v w with the rdac configured as a potentiometer divider similar to a voltage output dac. v a = v dd and v b = 0 v. dnl specification limits of 1 lsb maximum are guaranteed monotonic operating conditions. 6 resistor terminal a, resistor terminal b, and resistor terminal w have no limitations on polarity with respect to each other. 7 guaranteed by design , but not subject to production test. 8 p diss is calculated fro m (i dd v dd ). cmos logic level inputs result in minimum power dissipation. 9 all dynamic characteristics use v dd = 5 v.
ad5162 rev. c | page 4 of 20 electrical character istics : 10 k? , 50 k? , and 100 k? versions v dd = 5 v 10%, or 3 v 10%; v a = v dd ; v b = 0 v; ?40c < t a < 125c; unless otherwise noted. table 2 . parameter symbol conditions min typ 1 max unit dc ch aracteristics rheostat mode resistor differential nonlinearity 2 r- dnl r wb , v a = no connect ? 1 0.1 +1 lsb resistor integral nonlinearity 2 r- inl r wb , v a = no connect ? 2.5 0.25 +2.5 lsb nominal resistor tolerance 3 ?r ab t a = 25c ? 20 +20 % resistance temperature coefficient ( ?r ab /r ab )/ ?t v ab = v dd , wiper = no connect 35 ppm/c wiper resistance r wb code = 0x00, v dd = 5 v 160 200 ? dc characterist ics potentiometer divider mode 4 di fferential nonlinearity 5 dnl ? 1 0.1 +1 lsb integral nonlinearity 5 inl ? 1 0.3 +1 lsb voltage divider temperature coefficient ( ?v w /v w )/ ?t code = 0x80 15 ppm/c full - scale error v wfse code = 0xff ? 2.5 ? 1 0 lsb zero - scale error v wzse code = 0x00 0 1 2.5 lsb resistor terminals voltage range 6 v a , v b , v w gnd v dd v capacitance a, b 7 c a , c b f = 1 mhz, measured to gnd, code = 0x80 45 pf capacitance w 7 c w f = 1 mhz, measured to gnd, code = 0x80 60 pf common - mode leakage i cm v a = v b = v dd /2 1 na digital inputs and outputs input logic high v ih v dd = 5 v 2.4 v input logic low v il v dd = 5 v 0.8 v input logic high v ih v dd = 3 v 2.1 v input logic low v il v dd = 3 v 0.6 v input current i il v in = 0 v or 5 v 1 a input capacitance c il 5 pf power supplies power supply range v dd range 2.7 5.5 v supply current i dd v ih = 5 v or v il = 0 v 3.5 6 a power dissipation p diss v ih = 5 v or v il = 0 v, v dd = 5 v 30 w power supply sensitivity pss v dd = 5 v 10%, code = midscale 0.02 0.08 %/% dynamic characteristics bandwidth , ? 3 db bw r ab = 10 k ? /50 k ? /100 k ? , code = 0x80 600/100/40 khz total harmonic distortion thd w v a = 1 v rms, v b = 0 v, f = 1 khz, r ab = 10 k ? 0.1 % v w settling time t s v a = 5 v, v b = 0 v, 1 lsb error band 2 s resistor noise voltage density e n_wb r wb = 5 k ? , r s = 0 9 nv / hz 1 typical specifications represent average readings at 25c and v dd = 5 v. 2 resistor position nonlinearity error , r- inl , is the deviat ion from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. r - dnl measures the relative step change from the ideal between successive tap positions. parts are guaranteed monotonic. 3 v a = v dd , v b = 0 v, wiper (v w ) = no connect. 4 specifications apply to all vrs . 5 inl and dnl are measured at v w with the rdac configured as a potentiometer divider similar to a voltage output dac. v a = v dd and v b = 0 v. dnl specification limits of 1 lsb maximum are guaranteed monotonic operating conditions. 6 resistor te rminal a, resistor te rminal b, and resistor te rminal w have no limitations on polarity with respect to each other. 7 guaranteed by design , but not subject to production test.
ad5162 rev. c | page 5 of 20 timing characteristi cs: all versions v dd = 5 v 10%, or 3 v 10%; v a = v dd ; v b = 0 v; ?40c < t a < +125c; unless otherwise noted. table 3 . parameter symbol conditions min typ max unit spi interface timing characteristi cs 1 clock frequency f clk 25 mhz input clock pulse width t ch , t cl clock level high or low 20 ns data setup time t ds 5 ns data hold time t dh 5 ns cs t css setup time 15 ns cs t csw high pulse widt h 40 ns clk fall to cs t csh0 fall hold time 0 ns clk fall to cs t csh1 rise hold time 0 ns cs t cs1 rise to clock rise setup 10 ns 1 see the timing diagrams for the lo cations of measured values (that is, see figure 42 and figure 43 ).
ad5162 rev. c | page 6 of 20 absolute maximum rat ings t a = 25c, unless otherwise noted. table 4 . parameter rating v dd to gnd C 0.3 v to +7 v v a , v b , v w to gnd v dd terminal current, ax to bx, ax to wx, bx to wx 1 pulsed 20 ma continuous 5 ma digital inputs and output voltage to g nd 0 v to 7 v operating temperature range C 40c to +125c maximum junction temperature (t jmax ) 150c storage temperature C 65c to +150c lead temperature (soldering, 10 sec) 300c thermal resistance, ja for 10- lead msop 2 230c/w 1 the m ax imum terminal current is bound by the maximum current handling of the switches, the maximum power dissipation of the package, and the maximum applied voltage across any two of the a, b, and w terminals at a given resistance. 2 the p ackage power dissipation is (t jmax ? t a )/ ja . stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ad5162 rev. c | page 7 of 20 pin configuration and function descri ptions 10 9 8 7 1 2 3 4 b1 a1 w2 w1 b2 cs sdi gnd 6 5 clk v dd top view ad5162 04108-0-002 figure 2. table 5 . pin function descriptions pin o. nemonic description 1 b1 b1 terminal. 2 a1 a1 terminal. 3 w2 w2 terminal. 4 gnd digital ground. 5 v dd positive power suppl y. 6 clk serial clock input. positive - edge triggered. 7 sdi serial data input. 8 cs chip select input, active low. when cs returns high, data is loaded into the dac register. 9 b2 b2 terminal. 10 w 1 w1 terminal.
ad5162 rev. c | page 8 of 20 typical performance characteristics ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 rheostat mode inl (lsb) 1.0 1.5 2.0 128 96 32 64 0 160 192 224 256 code (decimal) 04108-0-003 v dd = 5.5v t a = 25c r ab = 10k? v dd = 2.7v figure 3. r - inl vs. code vs. supply voltages ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 rheostat mode dnl (lsb) 128 96 32 64 0 160 192 224 256 code (decimal) 04108-0-004 t a = 25c r ab = 10k? v dd = 2.7v v dd = 5.5v figure 4. r - dnl vs. code vs. supply voltages ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 potentiometer mode inl (lsb) 128 96 32 64 0 160 192 224 256 code (decimal) 04108-0-005 r ab = 10k? v dd = 2.7v t a = ?40c, +25c, +85c, +125c v dd = 5.5v t a = ?40c, +25c, +85c, +125c figure 5 . inl vs. code vs. temperature ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 potentiometer mode dnl (lsb) 128 96 32 64 0 160 192 224 256 code (decimal) 04108-0-006 v dd = 2.7v; t a = ?40c, +25c, +85c, +125c r ab = 10k? figure 6 . dnl vs. code vs. temperature ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 potentiometer mode inl (lsb) 128 96 32 64 0 160 192 224 256 code (decimal) 04108-0-007 t a = 25c r ab = 10k? v dd = 2.7v v dd = 5.5v figure 7 . inl vs. code vs. supply voltages ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 potentiometer mode dnl (lsb) 128 96 32 64 0 160 192 224 256 code (decimal) 04108-0-008 t a = 25c r ab = 10k? v dd = 2.7v v dd = 5.5v figure 8 . dnl vs. code vs. supply voltages
ad5162 rev. c | page 9 of 20 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 rheostat mode inl (lsb) 1.0 1.5 2.0 128 96 32 64 0 160 192 224 256 code (decimal) 04108-0-009 r ab = 10k? v dd = 2.7v t a = ?40c, +25c, +85c, +125c v dd = 5.5v t a = ?40c, +25c, +85c, +125c figure 9. r - inl vs. code vs. temperature ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 rheostat mode dnl (lsb) 128 96 32 64 0 160 192 224 256 code (decimal) 04108-0-010 v dd = 2.7v, 5.5v; t a = ?40c, +25c, +85c, +125c r ab = 10k? figure 10 . r - dnl vs. code vs. temperature ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 fse, full-scale error (lsb) 1.0 1.5 2.0 temperature (c) ?40 ?25 ?10 5 20 35 50 65 80 95 110 125 04108-0-011 v dd = 5.5v, v a = 5.0v r ab = 10k? v dd = 2.7v, v a = 2.7v figure 11 . full - scale error vs. temperature 0 0.75 1.50 2.25 3.00 3.75 4.50 zse, zero-scale error (lsb) temperature (c) ?40 ?25 ?10 5 20 35 50 65 80 95 110 125 04108-0-012 v dd = 5.5v, v a = 5.0v r ab = 10k? v dd = 2.7v, v a = 2.7v figure 12 . zero - scale error vs. temperatur e i dd , supply current ( a) 0.1 1 10 ?40 ?7 26 59 92 125 temperature (c) 04108-0-013 v dd = 5v v dd = 3v figure 13 . supply current vs. temperature ?20 0 20 40 60 80 100 120 rheostat mode tempco (ppm/c) 128 96 32 64 0 160 192 224 256 code (decimal) 04108-0-014 r ab = 10k? v dd = 2.7v t a = ?40c to +85c, ?40c to +125c v dd = 5.5v t a = ?40c to +85c, ?40c to +125c figure 14 . rheostat mode tempco r wb / t vs. code
ad5162 rev. c | page 10 of 20 ?30 ?20 ?10 0 10 20 potentiometer mode tempco (ppm/c) 30 40 50 128 96 32 64 0 160 192 224 256 code (decimal) 04108-0-015 r ab = 10k? v dd = 2.7v t a = ?40c to +85c, ?40c to +125c v dd = 5.5v t a = ?40c to +85c, ?40c to +125c figure 15 . potentiometer mode tempco v wb / t vs. code ?60 ?54 ?48 ?42 ?36 ?30 ?24 ?18 ?12 ?6 0 gain (db) frequency (hz) 10k 1m 100k 10m 04108-0-016 0x80 0x40 0x20 0x10 0x08 0x04 0x01 0x02 figure 16 . gain vs. frequency vs. code, r ab = 2.5 k ? ?60 ?54 ?48 ?42 ?36 ?30 ?24 ?18 ?12 ?6 0 gain (db) frequency (hz) 1k 100k 10k 1m 04108-0-017 0x80 0x40 0x20 0x10 0x08 0x04 0x01 0x02 figure 17 . gain vs. frequency vs. code, r ab = 10 k ? ?60 ?54 ?48 ?42 ?36 ?30 ?24 ?18 ?12 ?6 0 gain (db) frequency (hz) 1k 100k 10k 1m 04108-0-018 0x80 0x40 0x20 0x10 0x08 0x04 0x01 0x02 figure 18 . gain vs. frequency vs. code, r ab = 50 k ? ?60 ?54 ?48 ?42 ?36 ?30 ?24 ?18 ?12 ?6 0 gain (db) frequency (hz) 1k 100k 10k 1m 04108-0-019 0x80 0x40 0x20 0x10 0x08 0x04 0x01 0x02 figure 19 . gain vs. frequency vs. code, r ab = 100 k ? ?60 ?54 ?48 ?42 ?36 ?30 ?24 ?18 ?12 ?6 0 gain (db) frequency (hz) 10k 1k 100k 1m 10m 04108-0-020 100k ? 60khz 50k? 120khz 10k ? 570khz 2.5k? 2.2mhz figure 20 . ? 3 db bandwidth at code = 0x80
ad5162 rev. c | page 11 of 20 i dd , supply current (ma) 0.01 1 0.1 10 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 digital input voltage (v) 04108-0-025 t a = 25c v dd = 2.7v v dd = 5.5v figure 21 . supply current vs. digital input voltage 04108-0-021 v w clk figure 22 . digital feedthro ugh 04108-0-022 v w2 v w1 figure 23 . digital crosstalk 04108-0-024 v w2 v w1 figure 24 . analog crosstalk 04108-0-026 v w figure 25 . midscale glitch, code 0x80 to code 0x7f 04108-0-023 v w cs figure 26 . large - signal settling time
ad5162 rev. c | page 12 of 20 test circuits figure 27 through figure 32 illustrate the test circuits that define the test conditions used in the product specification tables (see table 1 and table 2 ). 04108-0-027 v ms a w b dut v+ v+ = v dd 1lsb = v+/2 n figure 27 . test circuit for potentiometer divider nonlinearity error (inl, dnl) 04108-0-028 no connect i w v ms a w b dut figure 28 . test circuit for resistor position nonlinearity error (rheostat operation : r- inl, r - dnl) 04108-0-029 v ms2 v ms1 v w a w b dut i w = v dd /r nominal r w = [v ms1 ? v ms2 ]/i w figure 29 . test circuit for wiper resistance 04108-0-030 ?v ms % dut ( ) a w b v+ ?v dd % ?v ms ?v dd ?v dd v a v ms v+ = v dd 10% psrr (db) = 20 log pss (%/%) = figure 30 . test circuit for power supply sensitivity (pss, pssr) 04108-0-031 +15v ?15v w a 2.5v b v out offset gnd dut ad8610 v in figure 31 . test circuit for gain vs. frequen cy w b v cm i cm a nc gnd nc v dd dut nc = no connect 04108-0-033 figure 32 . test circuit for common - mode leakage current
ad5162 rev. c | page 13 of 20 theory of operation the ad5162 is a 256 - position , digitally controlled variable resistor (vr) device. an internal power - on preset places the wiper at midscale duri ng power - on, which simplifies the fault condition recovery at power - up. programming the vari able resistor and voltage rheostat operation the nominal resistance of the rdac between terminal a and terminal b is available in 2.5 k ?, 10 k?, 50 k?, and 100 k?. the nominal resistance (r ab ) of the vr has 256 contact points acce ssed by the wiper terminal and the b terminal contact. the 8- bit data in the rdac latch is decoded to select one of the 256 possible setting s. a w b a w b a w b 04108-0-034 figure 33 . rheostat mode configuration assuming that a 10 k ? part is used, the first connection of the wiper starts at the b terminal for data 0x00. because there is a 50 ? wiper contact resistance, such a connection yields a minimum of 100 ? (2 50 ?) resistance between terminal w and terminal b . the second connection is the first tap point, which corresponds to 139 ? (r wb = r ab /256 + 2 r w = 39 ? + 2 50 ?) for data 0x01. the third connection is the next tap point, repre senting 178 ? (2 39 ? + 2 50 ?) for data 0x02, and so on. each lsb data value increase moves the wiper up the resistor ladder until the last tap point is reached at 10,100 ? (r ab + 2 r w ). d5 d4 d3 d7 d6 d2 d1 d0 rdac latch and decoder r s r s r s r s a w b 04108-0-035 figure 34 . ad5162 equivalent rdac circuit the general equation determining the digitally programmed output resistance between w and b is w ab wb rr d dr += 2 256 )( (1) where: d is the decimal equivalent of the binary code loaded in the 8- bit rdac register. r ab is the end - to - end resistance. r w is the wiper resistance contributed by the on resistance of the internal switch. in summary, if r ab is 10 k ? and the a terminal is open circuited, the output resistance , r wb , is set according to the rdac latch codes , as listed in table 6 . table 6 . codes and corresponding r wb resistance d (dec) r wb (? ) ou tput state 255 9 961 full scale (r ab ? 1 lsb + r w ) 128 5 060 midscale 1 139 1 lsb 0 100 zero scale (wiper contact resistance) note that in the zero - scale condition, a finite wiper resistance of 100 ? is present. care should be taken to lim it the current flow between w and b in this state to a maximum pulse current of no more than 20 ma. otherwise, degradation or possible destruc tion of the internal switch contact may occur. similar to the mechanical potentiometer, the resistance of the rd ac between wiper w and terminal a also produces a digitally controlled complementary resistance , r wa . when these terminals are used, the b terminal can be opened. setting the resistance value for r wa starts at a maximum value of resistance and decreases as the data loaded in the latch increases in value. the general equation for this operation is w ab wa rr d dr + ? = 2 256 256 )( (2) when r ab is 10 k ? and the b terminal is open circuited, the output resistance , r wa , is set according to the rdac latch codes , as liste d in table 7 . table 7 . codes and corresponding r wa resistance d (dec) r wa (? ) output state 255 139 full scale 128 5 060 midscale 1 9 961 1 lsb 0 10,060 zero scale typical devic e- to - devi ce matching is process - lot dependent and may vary by up to 30%. because the resistance el ement is processed in thin - film technology, the change in r ab with tem - perature has a very low temperature coefficient of 35 ppm/c.
ad5162 rev. c | page 14 of 20 programming the potentiometer di vider voltage output operation the digital potentiometer easily generates a voltage divider at wiper to b and wiper to a, proportional to the input voltage at a to b. unlike the polarity of v dd to gnd, which must be positive, voltage across a to b, w to a, and w to b can be at either polarity. a v i w b v o 04108-0-036 figure 35 . potentiometer mode configuration if ignoring the effect of the wiper resistance for approximation, connecting the a terminal to 5 v and the b terminal to ground produces an output voltage at the wiper to b, starting at 0 v up to 1 lsb less than 5 v. each lsb of voltage is equal to the voltage applied across the a and b terminal s divided by the 256 positions of the potentiometer divider. the general equation defining the output volt age at v w with respect to ground for any valid in put voltage applied to terminal a and terminal b is b a w v d v d dv 256 256 256 )( ? += (3) a more accurate calculation, which includes the effect of wiper resistance, v w , is b ab wa a ab wb w v r dr v r dr dv )( )( )( + = (4) operation of th e digital potentiometer in the divider mode r esults in more accurate operation over temperature. unlike in the rheostat mode, the output voltage is dependent mainly on the ratio of the internal resistors r wa and r wb , not on the absolute values. therefore, the temperature drift reduces to 15 ppm/c. esd protection all digital inputs are protected with a series of input resistors and parallel zener esd structures, as shown in figure 36 and fig ure 37 . this applies to the sdi, clk, and cs logic 340? gnd 04108-0-037 digital input pins. figure 36 . esd protection of digital pins a, b, w gnd 04108-0-038 figure 37 . esd protection of resistor terminals terminal voltage ope rati ng range the ad5162 v dd and gnd power supply defines the boundary conditions for proper 3 - terminal digital potentiometer opera - tion. supply signals present on the a, b, and w terminals that exceed v dd or gnd are clamped by the internal forward - biased diode s (see figure 38). gnd a w b v dd 04108-0-039 figure 38 . maximum terminal voltages set by v dd and gnd power - up sequence because the esd protection diodes limit the voltage compliance at the a, b, and w terminals (see figure 38 ), it is important to power v dd /gnd before applying voltage to the a, b, and w terminals; otherwise, the diode is forward - biased such that v dd is powered unintentionally and may affect the rest of the users circuit. the ideal power - up sequence is in the following order: gnd, v dd , digital inputs, and then v a , v b , v w . the relative order of powering v a , v b , v w , and the digital inputs is not important , as long as they are powered after v dd /gnd.
ad5162 rev. c | page 15 of 20 layout and power supply bypassing it is good practice to employ compact, minimum lead length layout design. the leads to the inputs should be as direct as possible with a minimum conductor length. ground paths should have low resistance and low inductance. similarly, it is also good practice to bypass the power supplies with quality capacitors for optimum stability. supply leads to the device should be bypassed with disc or chip ceramic capacitors of 0.01 f to 0.1 f. low esr 1 f to 10 f tantalum or electrolytic capacitors should also be applied at the supplies to minimize any transient disturbance and low frequency ripple (see figure 39). in addition, note that the digital ground should be joined remotely to the analog ground at one point to minimize the ground bounce. v dd gnd v dd c3 10 ? f c1 0.1 ? f ad5162 + 04108-0-040 figure 39. power supply bypassing constant bias to retain resistance setting for users who desire nonvolatility but cannot justify the additional cost of the eemem, the ad5162 can be considered a low cost alternative by maintaining a constant bias to retain the wiper setting. the ad5162 is designed specifically for low power applications, allowing low power consumption even in battery- operated systems. the graph in figure 40 demonstrates the power consumption from a 3.4 v, 450 mahr li-ion cell phone battery connected to the ad5162. the measurement over time shows that the device draws approximately 1.3 a and consumes negligible power. over a course of 30 days, the battery is depleted by less than 2%, the majority of which is due to the intrinsic leakage current of the battery itself. this demonstrates that constantly biasing the potentiometer can be a practical approach. most portable devices do not require the removal of batteries for the purpose of charging. although the resistance setting of the ad5162 is lost when the battery needs replacement, such events occur rather infrequently such that this inconvenience is justified by the lower cost and smaller size offered by the ad5162. if total power is lost, the user should be provided with a means to adjust the setting accordingly. days battery life depleted (%) 0 90 92 94 96 51015 98 100 102 104 106 108 110 20 25 30 04108-0-041 t a = 25 c figure 40. battery operating life depletion evaluation board an evaluation board, along with all necessary software, is available to program the ad5162 from any pc running windows? 98/2000/xp. the graphical user interface, as shown in figure 41, is straightforward and easy to use. more detailed information is available in the user manual, which is supplied with the board. 04108-0-044 figure 41. ad5162 evaluation board software the ad5162 starts at midscale upon power-up. to increment or decrement the resistance, simply move the scrollbars in the left of the software window (see figure 41). to write a specific value, use the bit pattern in the upper part of the sdi write bit control (hit run) box and then click run . the format of writing data to the device is shown in table 8.
ad5162 rev. c | page 16 of 20 spi interface spi-compatible, 3-wire serial bus the ad5162 contains a 3-wire, spi-compatible digital interface (sdi, cs , and clk). the 9-bit serial word must be loaded msb first. the format of the word is shown in table 8. the positive-edge sensitive clk input requires clean transitions to avoid clocking incorrect data into the serial input register. standard logic families work well. if mechanical switches are used for product evaluation, they should be debounced by a flip-flop or another suitable means. when cs is low, the clock loads data into the serial register on each positive clock edge (see figure 42). the data setup and data hold times in table 3 determine the valid timing requirements. the ad5162 uses a 9-bit serial input data register word that is transferred to the internal rdac register when the cs line returns to logic high. extra msb bits are ignored. table 8. serial data-word format 1 msb lsb b8 b7 b6 b5 b4 b3 b2 b1 b0 a0 d7 d6 d5 d4 d3 d2 d1 d0 (2 8 ) (2 7 ) (2 0 ) 1 the values of bits are shown in parentheses. sdi clk cs v out rdac register load a0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 0 1 0 0 1 1 04108-0-042 figure 42. spi interface timing diagram (v a = 5 v, v b = 0 v, v w = v out ) t csh0 t css t cl t ch t ds t csw t s t cs1 t csh1 t ch clk cs v out 1 0 1 0 1 0 v dd 0 1lsb sdi (data in) dx dx 04108-0-043 figure 43. spi interface detailed timing diagram (v a = 5 v, v b = 0 v, v w = v out )
ad5162 rev. c | page 17 of 20 outline dimensions compliant to jedec standa rds m o-187-ba 091709-a 6 0 0.70 0.55 0.40 5 10 1 6 0.50 bsc 0.30 0.15 1.10 max 3.10 3.00 2.90 co planar ity 0.10 0.23 0.13 3.10 3.00 2.90 5.15 4 .90 4.65 pin 1 identifier 15 max 0.95 0.85 0.75 0.15 0.05 figure 44 . 10 - lead mini small outline package [msop] (rm - 10) dimension s shown in millimeters ordering guide model 1 , 2 , 3 r ab (k ?) temperature package description package option branding ad5162brm2.5 2.5 C 40c to +125c 10- lead msop rm - 10 d0q ad5162brm2.5 - rl7 2.5 C 40c to +125c 10- lead msop rm - 10 d0q ad5162brm10 10 C4 0c to +125c 10- lead msop rm - 10 d0r ad5162brm50 50 C 40c to +125c 10- lead msop rm - 10 d0s ad5162brm50 - rl7 50 C 40c to +125c 10- lead msop rm - 10 d0s ad5162brm100 100 C 40c to +125c 10- lead msop rm - 10 d0t ad5162brm100 - rl7 100 C 40c to +125c 10- lea d msop rm - 10 d0t ad5162brmz2.5 2.5 C 40c to +125c 10- lead msop rm - 10 d74 ad5162brmz2.5 - rl7 2.5 C 40c to +125c 10- lead msop rm - 10 d74 ad5162brmz10 10 C 40c to +125c 10- lead msop rm - 10 d9k ad5162brmz10 - rl7 10 C 40c to +125c 10- lead msop rm - 10 d9k ad5162brmz50 50 C 40c to +125c 10- lead msop rm - 10 d0s# ad5162brmz50 - rl7 50 C 40c to +125c 10- lead msop rm - 10 d0s# ad5162brmz100 100 C 40c to +125c 10- lead msop rm - 10 d0t# ad5162brmz100 - rl7 100 C 40c to +125c 10- lead msop rm - 10 d0t# ad5162wbrmz100 - rl7 100 C 40c to +125c 10- lead msop rm - 10 d0t# ad5162eval evaluation board 1 z = rohs compliant part. 2 w = qualified for automotive applications. 3 the evaluation board is shipped with the 10 k ? r ab resistor opti on; however, the board is compatible with all available resistor value options. a utomotive products the ad 5162 w model is available with controlled manufacturing to support the quality and reliability requirements of automotive applications. note t hat these automotive models may have specifications that differ from the commercial models; therefore, designers should review the specifications section of this data sheet carefully. only the automotive grade products shown are available for use in automo tive applications. contact your local analog devices account representative for specific product ordering information and to obtain the specific automotive reliability reports for these models.
ad5162 rev. c | page 18 of 20 notes
ad5162 rev. c | page 19 of 20 notes
ad5162 rev. c | page 20 of 20 notes ? 2003 C 2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d04108 -0- 12/10(c)

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